The present invention relates to integrated circuit devices, and more particularly, to antifuse circuits in memory devices.
Typical integrated memory devices include arrays of memory cells arranged in rows and columns. In many such memory devices, several redundant rows and columns are provided to replace malfunctioning memory cells found during testing. Testing is typically performed by having predetermined data values written to selected row and column addresses that correspond to memory cells. The memory cells are then read to determine if the data read matches the data written to those memory cells. If the read data does not match the written data, then those memory cells are likely to contain defects which will prevent proper operation of the memory device.
The defective memory cells may be replaced by enabling the redundant circuitry. A malfunctioning memory cell in a column or a row is substituted with an entire column or row of redundant memory cells. Therefore, a memory device need not be discarded even though it contains defective memory cells. Substitution of one of the redundant rows or columns is accomplished in a memory device by programming a specific combination of fuses, or if the memory device uses antifuses, by programming a specific combination of antifuses, located in one of several fuse or antifuse blocks in the memory device. Conventional fuses are resistive devices which may be opened or broken with a laser beam or an electric current. Antifuses are capacitive devices that may be closed or blown by breaking down a dielectric layer in the antifuse with a relatively high voltage.
A specific combination of antifuses are programmed to correspond to an address of a row or column having defective memory cells. For example, if the defective row or column has a 12-bit binary address of 100100100100, then the antifuses in a set of 12 antifuses are programmed to store this address. Antifuses are typically arranged in an antifuse bank with the number of antifuses corresponding to the number of address bits for a row or column address. The memory device contains several antifuse banks so that several redundant rows and columns can be substituted for defective memory cells.
When the programmed redundant address is detected by the memory device, the redundant row or column is accessed instead of the row or column having the defective memory cells. The antifuse bank compares the incoming addresses to the redundant addresses programmed by the antifuses, and determines whether there is a match. If a match is detected, then the corresponding antifuse bank outputs a match signal. The match signal indicates that a redundant row or column should be accessed, and the defective row or column should be ignored.
A problem with conventional antifuse banks is that they occupy a significant amount of the total layout area of a memory device. This is a result of the current design of conventional antifuse banks. Each antifuse of the antifuse bank includes circuitry dedicated to programming and comparing that one antifuse. As shown in FIG. 1, a conventional antifuse bank 10 includes several antifuse circuits 12a-g. There is one antifuse circuit 12 for each address bit of a row or column address A0-Am. Each antifuse circuit 12a-g includes the same elements. In particular, an antifuse 16, a programming circuit 18 for programming the antifuse 16, and a comparing circuit 20 that compares a respective bit of the incoming address to the programmed state of the corresponding antifuse 16. Conventional antifuse comparing and programming circuits are well known in the art and do not need to be discussed in detail herein. The comparing circuit 20 generates a high COMP signal when the respective bit of the incoming address matches the programmed state of the antifuse 16. Each comparing circuit provides a COMP signal to a judgment circuit 24 that generates a MATCH signal when all of the antifuse circuits 12a-g provide a high COMP signal.
As illustrated by FIG. 1, the structure of a conventional antifuse bank 10 consists of the same basic circuitry repeated for each bit of a row or column address. In the case of the programming circuit 18, which has several transistors having physically large dimensions because of the high current necessary to program an antifuse, having one programming circuit 18 for each antifuse 16 requires a significant portion of the overall layout area of a memory device. Another consideration is that, as the number of memory cells for a memory device continues to increase, additional address bits will be required to access the memory cells. Consequently, antifuse circuits 12 corresponding to the additional address bits will also be required to facilitate replacement of any defective memory cells, thus further increasing the layout area occupied by an antifuse bank 10.
The present invention is directed to a method and apparatus for detecting a digital word on a plurality of signal lines matching a bit pattern programmed by a corresponding plurality of fusible devices. A detector circuit comprises decoder circuits coupled between first and second sense nodes and a reference node, and an evaluation circuit also coupled to the first and second sense nodes to generate a match signal indicative of detecting the digital word. The decoder circuits may comprise a fusible device and a switch, where closing the switch of a programmed fusible device will change the voltage of the sense node to which the decoder circuit is coupled. The evaluation circuit senses the voltage of both sense nodes and produces a match signal according to these voltages. An enable circuit may also be coupled to the detector circuit to either enable or disable operation of the detector circuit based on whether the enable circuit has been programmed.